This invention relates generally to initializing a programmable logic device, and more particularly to methods, systems, and computer program products for using direct memory access to initialize a programmable logic device.
Many computer/electronic systems use programmable logic devices (PLDs) configured to perform application specific functions. PLDs may include a wide range of programmable logic devices such as programmable logic arrays (PLAs), programmable array logic (PAL), generic logic arrays (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), and other technologies known in the art. A number of PLD technologies are field programmable, such as FPGAs, and such devices may require programming each time they are powered on. PLDs that require reprogramming on each depower/power cycle are typically referred to as “volatile” PLDs, and may rely upon static random access memory (SRAM) for a programmed device configuration while powered. Volatile PLDs may also need periodic refreshing or may require reprogramming if a transient or “soft” (recoverable) error occurs. Soft errors may result from environmental effects such as electromagnetic interference (EMI), cosmic rays, alpha particles, thermal neutrons, noise, and other similar sources.
Systems that include volatile PLDs are often designed to support frequent reprogramming, a technique referred to as “reconfigurable computing”. In a system employing reconfigurable computing, the time required to program a PLD can be a critical factor in system performance and overall responsiveness. In such a system, there may be multiple PLD programs that must be loaded as part of system initialization, resulting in a long system initialization time.
A PLD may be programmed in the field without the use of special test equipment interfaces, such as board-level or component-level loaders with joint test action group (JTAG) compliant interfaces. Access to a JTAG port on a PLD is usually limited to a manufacturing or test facility. “Field programming” may include programming in a closed system at customer facility or at a location external to a manufacturer, where access to special test equipment is limited or infeasible. Programming techniques available without special test equipment may also be performed at a manufacturing or test facility.
In one method of programming a PLD in the field, the PLD automatically loads its configuration from a serial electronically erasable programmable read-only memory (EEPROM) or flash memory device. Each PLD may have a dedicated serial EEPROM directly coupled to the PLD as a discrete component on the same system board. This method of programming has been referred to as “active serial” programming or loading. Active serial programming may provide benefits in that the specific program for each PLD can be isolated to minimize the risk of mismatching a PLD program with a targeted PLD. However, active serial programming can be slow if the serial programming speed is slow, particularly when the bit rate is low relative to the associated programming clock speed (e.g., one bit per clock cycle). A PLD utilizing active serial programming may start to load its PLD program whenever the PLD is released from reset, which can complicate the reset design of the system. Complications can arise if other system components are not intended to be reset whenever the PLD program is loaded. Active serial programming can present a number of other issues, such as version control management of the PLD program in the serial EEPROM, particularly in updating and verifying the correct/latest version of the PLD program. Serial EEPROMs may not support field reprogramming, requiring board rework or physical part replacement for a socketed serial EEPROM component. Errors or failures in serial EEPROMs may also be difficult to detect and isolate, resulting in an increased number of system failure modes. The use of serial EEPROMs may have additional penalties in cost, board area, power consumption, heat, weight, and obsolescence issues in the manufacturing process.
Another method of programming a PLD in the field is through external programming actively controlled by a processor. PLD programming may be carried out by a general-purpose processor through data bus writes, and PLD control signals may be manipulated via a software program executing upon the processor. The processor typically reads the PLD programming data, writes the data directly on a data bus to the PLD one byte at a time, and manipulates the appropriate control signals such that the PLD accepts the data as programming information. Although actively controlling the PLD programming process through the processor may provide flexibility, PLD programming may consume the processor's bandwidth for a significant duration, particularly if the PLD programming file is large. While the processor is busy actively programming the PLD, the processor must wait to perform other system initialization tasks, causing an extended time delay to initialize an entire system. If there are multiple PLDs in the system with different PLD programs, the problem is further compounded, as the processor may not perform other tasks while its resources are dedicated to programming the PLDs.
As the size of PLD programming files continues to grow with the development of more advanced technologies, the demand on a processor performing active PLD programming will continue to increase, resulting in a longer system initialization time. Furthermore, larger PLD programming files will impact the required storage capacity of serial EEPROMs, potentially resulting in larger components, longer programming time, and a higher system cost. Accordingly, there is a need in the art for a method of programming of a PLD without relying upon direct active control by a processor or active serial programming.